[PATCH i386 AVX512] [65/n] Add rest of VI1-AVX2: mul insn pattern.

[Kirill Yukhin]

Hello,
This tiny patch extend mul<mode> insn pattern to support
masking.

Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.

Is it ok for trunk?

gcc/
* config/i386/sse.md
(define_expand "mul<mode>3<mask_name>"): Add masking.

--
Thanks, K

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 594e692..a3b2477 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -9238,11 +9238,11 @@
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "TI")])

-(define_expand "mul<mode>3"
+(define_expand "mul<mode>3<mask_name>"
[(set (match_operand:VI1_AVX2 0 "register_operand")
(mult:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand")
(match_operand:VI1_AVX2 2 "register_operand")))]
- "TARGET_SSE2"
+ "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
{
ix86_expand_vecop_qihi (MULT, operands[0], operands[1], operands[2]);
DONE;

[Uros Bizjak]

Post by Kirill Yukhin
Hello,
This tiny patch extend mul<mode> insn pattern to support
masking.
Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
* config/i386/sse.md
(define_expand "mul<mode>3<mask_name>"): Add masking.

OK.

Thanks,
Uros.